Micro-codable Discrete Wavelet Transform

avelet Transform has been successfully applied in different fields, ranging from pure mathematics to applied science. Numerous studies, carried out on Wavelet Transform, have proven its advantages in image processing and data compression and have made it a basic encoding technique in recent data compression standards. Pure software implementations of the Discrete Wavelet Transform, however, appears to be the performance bottleneck in real-time systems in terms of performance. Therefore, hardware acceleration of the DWT has become a topic of recent research. The goal of our research is to investigate the possibility of hardware acceleration of Discrete Wavelet Transform for image compression applications and to compare the performance improvement against the pure software implementation. In this thesis, we introduce a novel micro-architectural design for efficient hardware acceleration of the Discrete Wavelet Transform. The unit was designed to be integrated as an extension to the Instruction Set Architecture (ISA) of a microprocessor in a custom-computing platform like [1] and can be used to accelerate multimedia applications as JPEG2000 or MPEG-4. The design is based on the Fast Lifting Wavelet Transform scheme (FLWT), which is a fast implementation of the Discrete Wavelet Transform. The design utilizes various techniques such as pipelining, parallel execution, data reusability and specific features of the Xilinx Virtex II FPGAs to accelerate the transform. For performance analysis, a software package (Liftpack [2]) and a simulator (Sim-outorder of SimpleScalar toolset [3]) were used. The simulator was modified and the software was optimized for integer arithmetic for optimum software performance. This optimized version was used as benchmark to investigate the performance enhancement due to the hardware acceleration. The hardware unit operates with a clock frequency of 50 MHz. Assuming a processor clock frequency of 1 GHz for the software implementation, a speedup of over 5 times for a picture size of 720*560 was achieved. The performance will be even higher for pictures with larger dimensions or for filters of larger degrees. In addition, investigations show a much higher speedup capacity for popular filters like La Gill 5/3 or Daubechies 9/7 when they are factorized into Lifting steps and implemented with this design. Our conclusion is that the proposed design can substantially accelerate the DWT and the inherent scalability can be exploited to reach a higher performance in the future.